Increased semiconductor technology has provided for the ability to fabricate a large number of semiconductor devices on one single chip. Bipolar circuits typically provide fast gate speeds, reduced delay per unit load, and have historically been the predominate technology applied in integrated circuits. CMOS (complimentory metal-oxide-semiconductor) structures provide high noise immunity, high input impedance, and low power requirements, and have rapidly gained acceptance in the industry. However, a large CMOS structure is required when driving large capacitive loads and in most cases, several stages of scaled CMOS inverters are necessary in order to minimize the total delay. For BIMOS arrays having a large number of devices, it is desirable that each MOS device be of small size. As the size of a MOS device is reduced, the transconductance of the device and consequently the ability to drive a heavy capacitive load is also reduced. Bipolar devices continue to be used for driving these capacitive loads due to their high current gain. In quiesent periods, the bipolar push-pull transistors do not dissipate power. During transient periods, the bipolar current gain allows faster charging and discharging of capacitive loads. This results in a significant decrease in metal and fanout delays. Furthermore, smaller CMOS devices may be used in the BIMOS circuit than those required in an all-CMOS device circuit. Attempts to combine bipolar and MOS technology to achieve all of these results have been numerous in recent years.
One previously known circuit combining bipolar and MOS devices comprises a pair of push-pull NPN transistors. The upper NPN transistor has a collector connected to a first voltage source and the source of a P-channel device, an emitter connected to an output terminal and the collector of the lower NPN transistor, and a base connected to an input terminal and the gates of the P-channel device and an N-channel device. The lower NPN transistor has an emitter connected to a second voltage source and the source of the N-channel device, and a base connected to the drains of the P-channel and the N-channel devices. However, this circuit has a low impedance at the input terminal since the input terminal is connected to the base of the upper NPN transistor, and as the output switches from low to high, the lower transistor is slow to turn off causing a slow transition to the high output.
Another previously known circuit is described in U.S. patent application Ser. No. 647,216 and "BI-MOS Technology for High-Performance VLSI Circuits", VLSI DESIGN, page 98, August 1984. A BIMOS circuit comprises upper and lower NPN push-pull transistors having an output terminal coupled therebetween. A P-channel device has a source and a drain connected to the collector and base, respectively, of the upper transistor. An N-channel device has a source and drain connected to the base and collector, respectively, of the lower transistor. The gates of the P-channel and N-channel devices are connected to an input terminal.
Yet another previously known circuit is described in "CMOS Digital Technology", ELECTRONIC DESIGN, page 106, Oct. 4, 1984. Upper and lower NPN push-pull transistors have an output terminal coupled therebetween. A P-channel device has a source and drain connected to the collector and base, respectively of the lower NPN transistor. An N-channel device has a drain and source connected to the base and emitter, respectively, of the lower NPN transistor. The gates of the P-channel and N-channel devices and the base of the upper NPN transistor are connected to an input terminal. Although this circuit provides high input impedance, low power dissipation, high noise immunity, and high drive capability, the switching speed is not optimum.
Thus, what is needed is an integrated circuit combining, CMOS and bipolar technology having a high input impedance, improved switching characteristics, low power requirements, high noise immunity, high drive capability and improved power dissipation.